The present invention relates to automatic test equipment (ATE) for semiconductor device testing, and more specifically, to an apparatus, e.g. tester, for testing and measuring a semiconductor device, such as a memory and to a method of timing calibration. In particular, the invention relates to the accurate and automatic calibration of ATE input and output pin driver timing.
The present invention is particularly applicable to test equipment for testing semiconductor memories and logic to make possible the precise and continuous testing of logic and memory devices at wafer probe stage, or as dies or packaged parts, or in modules or circuits.
Test systems used for testing semiconductor devices should be able to test each new generation of devices at the maximum speed of the new device. A testing apparatus for a digital circuit generates various waveforms at a desired timing and detects the voltage level of the waveforms, usually comparing data read from the device under test with what is expected. The timing system is one of the most critical specifications of a tester. At present, typical systems provide a 60-ps resolution, 500-ps maximum driver-to-driver skewing and 700-ps maximum edge placement error. The overall timing accuracy is within xc2x11.5 ns. For the new generation of high-speed devices, the accuracy should be within a few hundred picoseconds. To achieve this increased accuracy, it is essential to calibrate the timing of the testing apparatus.
The invention is particularly appropriate for memory devices. Semiconductor memories tend to have a large number of input and output pins, for example, 36 pins, and are tested 16 or 32 at a time, requiring 36xc3x9732 tester pins. Consequently, the tester requires a large number of units of a per-pin structure, each of which needs timing calibration, since it is necessary to ensure that the timing of all voltage transitions delivered to the pins of the DUT, and the time at which data output from the device is compared with expected data, are accurate in relation to a defined reference. However, these transitions often occur at different times, due to the fact that signals travelling a channel path to a DUT must pass through cables, formatters, drivers and other devices having different electrical characteristics. The resulting timing variations are called xe2x80x9cskewxe2x80x9d. Generally, calibration involves measuring the skew in each system input and output channel and compensating for it by means of a variable delay in each channel (e.g., see U.S. Pat. No. 5,274,796). Hardware, software and a combination thereof can be used to control the compensating delay.
The traditional approach involves serially calibrating tester pin timing with respect to a reference pin or an external reference (see, e.g. U.S. Pat. No. 5,712,855). Since pin calibration measurements must be performed sequentially, an enormous amount of time is needed for this method. The amount of measured data required is also large; thus, the transfer and calculation time is undesirably long.
Another conventional approach which alleviates the above problems is described in U.S. Pat. No. 5,477,139, wherein the calibration is performed in parallel. This method shortens the time required for timing measurements, however, it increases the cost of the whole measuring apparatus, as it uses a number of local sequencers, one for each pin of the device under test (DUT).
Another means to execute the skew adjustment in parallel for all terminals of the IC tester is described in EP 356,967 A2. The disadvantage of the known method is that the skew adjustment is performed manually by an operator.
Another widely used calibration technique uses time domain reflectometry (TDR) based on transmission line theory. According to this theory, a wave travelling through a transmission line terminated by anything other than the line""s characteristic impedance is reflected back through the line. If the line terminates with an open circuit, the reflected wave equals the forwarded wave and this reflected wave is detected by the pin electronics. Using TDR techniques, automatic calibration circuits are provided to measure channel delays to the open circuited contact points of the tester. However, this approach has the disadvantage of requiring many delay compensation circuits per pin driver.
A method of autocalibrating a tester""s timings with respect to a common reference point is described in xe2x80x9cMaximizing and maintaining AC test accuracy in the manufacturing environmentxe2x80x9d by R. J. Bulaga and E. F. Westermann, Proceedings of the International Test Conference, Nashville, 1991, p.p. 976-985, IEEE. However, the known method is adapted for calibrating the skew of non-cyclic, e.g. asynchronous, test signals, requires the use of multiple bulk hardware and makes the system dense, and cost-ineffective. It takes about 30 seconds to perform a complete calibration, which is slow for conventional memories.
An automatic skew calibration circuit described in U.S. Pat. No. 5,384,781 provides a calibration technique for multi-channel signal sources using a means for varying the delay in response to a skew signal and determining a calibrated value for the delay. The circuit comprises a pair of cross-coupled flip-flops and a microprocessor. This method takes account of the variations in the time at which different flip-flops change state. It provides a fast calibration method which may be performed easily and frequently to correct the skew errors in signal sources. However, the technique becomes extremely complicated when the number of signal sources increases; moreover, it is not cost-effective in semiconductor memory test equipment with a large number of signal sources.
One of the main limitations of the known approaches to signal skew calibration is that the accuracy of measuring the signal skew decreases with the increasing speed and complexity of each new generation of high-speed synchronous devices. In a modern context, not only input/output signal skew compensation is needed, but also a significant improvement in the accuracy of measuring the skew itself, where there are multiple error sources and skew compensating delays. The necessity of increasing the accuracy of skew calibration creates a requirement for a fast, automatic calibration system providing extremely precise automatic calibration in test systems with multiple signal sources.
The object of the present invention is the provision of an ATE system that can perform highly accurate semiconductor testing by maintaining the precise timing characteristics of registers and providing precise calibration in relation to multiple signal sources, while at the same time reducing test time and tester cost and simplifying header characterization.
The advantage of the present invention is the ability of an ATE system using a skew calibration circuit incorporated in the tester""s header to reduce or substantially eliminate the timing skew between different signal sources and thus to enhance the accuracy of testing and provide acceptable and adequate testing of high-speed synchronous memory devices. According to the proposed invention, registers for latching data to and/or from the DUT are positioned in the test head or on the header, a card holding probe pins or sockets, to reduce the signal path to and/or from the DUT and thus avoid excessive distortion of the timing signal. Skew control may be performed by calibrating the tester""s registers only. The overall system is thus greatly simplified because it is not necessary to use programmable delays for each pin and the number of units to be calibrated is reduced, in comparison to conventional systems which require calibration of each pin driver. By using a common reference clock driver to calibrate the output registers, the delay between the moment when the register actually latches input data and the reference clock edge may be measured with greatly increased accuracy. An important advantage of the proposed system is that it also allows fast calibration to be carried with each DUT. This is especially important because various characteristics of a DUT itself may interfere with the operation of the registers and influence the accuracy of skew calibration.
The substance of the present invention is an automatic skew calibration means for skew calibration of a transceiver, for example, for calibrating the skew of signals transmitted to the DUT and received from the DUT in the course of a testing procedure, thus providing highly accurate testing of synchronous memory devices. The calibration is performed using a common time base which is available at different points on the calibration circuit, by which a reference signal is distributed from the reference clock source to the output registers.
The proposed means may be incorporated in the tester""s header or may be implemented as a separate unit connected to the tester""s header.
The number of input and output registers is defined by the number of registers in the DUT to be tested and may be one hundred or more. The registers may be implemented in, for example, but not limited to, flip-flops, latches or any other suitable means for latching signals.
A conventional clock generator may be used as a main clock source. The reference clock circuit may contain a plurality of phase shift means, e.g. a set of programmable delays, to provide a means for delaying the signal with respect to the main clock. The main clock source may be implemented, for example, by a PLL (Phase Lock Loop) clock generator, e.g. SY89429A manufactured by Synergy Semiconductor Corp. (U.S.A.), or by Analogue Devices, or similar fabrications by Vitalec or Edge Semiconductors.
The important feature of the present invention is that the DUT may be connected to the calibration means during the calibration operation, thereby allowing the electric characteristics of the DUT to be taken into account. The DUT characteristics, for example capacitance, may be measured after calibrating the tester. This feature is especially significant for CMOS logic, where timing is load capacitance dependent. Moreover, unlike conventional testers, which require the tester""s header to be changed whenever a new type of DUT is to be tested, the present invention allows the same tester to be used for testing different types of DUTs. In general, the proposed calibration means may be used for calibrating the timings of different systems for transmitting and receiving signals, typically called transceivers. A particular case of a transceiver is an electronic circuit tester for testing semiconductor devices.
Thus, in one aspect, the invention is an automatic skew calibration means for calibrating the timings of a transceiver, in particular, a semiconductor device testing apparatus, comprising:
a plurality of input registers for transmitting signals;
a plurality of output registers for receiving signals;
a main clock means for generating a main clock signal;
a reference clock means for supplying reference signals for calibrating the registers, the said reference clock means being associated with the said main clock means; and
a first plurality of phase shift means, comprising at least one set of phase shift means associated with each plurality of registers, for relative alignment of the register""s timing within each plurality.
The calibration means comprises a transmission line having predetermined wave characteristics, for distributing a reference signal from the reference clock means to the output registers.
Preferably, each the said set of phase shift means comprises at least one shift means associated with each separate register, for delaying the timing of that register.
To further enhance its accuracy, the skew calibration means preferably additionally comprises:
a second set of phase shift means associated with the said pluralities of registers, to allow the relative alignment of the register""s timing between the said pluralities,
the said plurality of input registers and the said plurality of output registers being connected to the main clock means via the second set of phase shift means. An important feature of the present invention is that the said plurality of output registers is operable to calibrate the said plurality of input registers.
Preferably, the said second set of phase shift means comprises at least one shift means associated with each plurality of registers.
Preferably, the said output registers are series-connected to the said reference clock means by the said transmission line.
Preferably, at least one or, more preferably, all of the components including the said plurality of input registers, the said plurality of output registers and the said reference clock means are parts of a tester header.
Another aspect of the present invention is a method of automatic transceiver skew calibration comprising:
calibrating a plurality of transceiver output registers with respect to a reference clock edge;
calibrating the propagation delay of the input registers of the transceiver using the calibrated output registers; and
relative alignment of the measured delays to the main clock edge.
Preferably, the method further comprises, before the said operation of calibrating the output registers, an operation of calibrating each programmable delay.
The method preferably further includes a step of increasing the accuracy of the test system in which the transceiver is used by determining the minimal feasible time delay between the reference clock edge and the moment when the register latches data. The calibration may be performed for each register or for pluralities of registers. It should also be noted that the measurements may be carried out for each bit of data transferred to or from the register.
Another aspect of the present invention is a test system for testing semiconductor devices comprising a timing means, a fault logic, and a central control unit, and also a set of input registers and a set of output registers, the said registers being calibrated using the calibration means and/or the calibration method proposed in the present invention. The test system may be calibrated in relation to a particular device under test to take into account the device characteristics that may interfere with the operation of the test system. Preferably the test system has the built-in calibration means proposed in the present invention. In particular, the calibration means may be incorporated in the tester""s header.
Another aspect of the present invention is a method of testing semiconductor devices including a step of transmitting a pattern of signals for accessing memory elements within the device, a step of receiving response signals for detecting failures in the memory elements and a step of processing test results, the method including a step of automatic skew calibration using the calibration means proposed in the present invention. Preferably, the skew calibration includes a step of determining the minimal feasible time delay between the reference clock edge and the moment when the register latches input data.
Still another aspect is a computer program for implementing, simulating or emulating the hardware functions of the skew calibration means or for computer implementation of the method in accordance with the present invention.